1. Field of the Invention
The present invention relates to a glitch suppressing apparatus, and more particularly, to a glitch suppressing apparatus for filtering positive glitches and negative glitches through a single circuit.
2. Description of Related Art
Conventional glitch suppressing methods mainly focus on suppressing positive glitches or negative glitches. FIG. 1 is a circuit diagram of a conventional positive glitch suppressing circuit. Referring to FIG. 1, the positive glitch suppressing circuit includes inverters 101, 103, and 107, delay circuits 102 and 105, and logic circuits 104 and 106, wherein the delay circuit 102 is used to delay an input signal S for a time t1, the delay circuit 105 is used to delay the positive edge of an output signal T of the logic circuit 104 for a time t2, and the logic circuits 104 and 106 are achieved by an OR gate and an AND gate respectively. Provided that the input signal S has a positive glitch with a width W, the timings of each of the signals in the positive glitch suppressing circuit are shown in FIGS. 2 and 3.
FIG. 2 shows the timings of each of the signals when the delay time t1 of the circuit shown in FIG. 1 is larger than the width W of the glitch. FIG. 3 shows the timings of each of the signals when the delay time t1 of the circuit shown in FIG. 1 is smaller than or equal to the width W of the glitch. As can be seen from FIG. 2 and FIG. 3, when the delay time t1 is larger than the width W of the glitch, the positive glitch suppressing circuit filters the positive glitches in the input signal S, as a result, an output signal V without any positive glitches is obtained. However, under the circumstance that the delay time t1 is smaller than or equal to the width W of the glitch, the positive glitch suppressing circuit cannot efficiently filter the positive glitches in the input signal S, as a result, the output signal V still has positive glitch noises.
FIG. 4 is a circuit diagram of a conventional negative glitch suppressing circuit. Referring to FIG. 4, the negative glitch suppressing circuit includes inverters 401, 403, and 407, delay circuits 402 and 405, logic circuits 404 and 406, wherein the delay circuit 402 is used to delay the input signal S for a time t2, the delay circuit 405 is used to delay the negative edge of an output signal U of the logic circuit 404 for a time t1, and the logic circuits 404 and 406 are achieved by an AND gate and an OR gate respectively. Provided that the input signal S has a negative glitch with a width W, the timings of each of the signals in the negative glitch suppressing circuit are shown in FIGS. 5 and 6.
FIG. 5 shows the timings of each of the signals when the delay time t2 of the circuit shown in FIG. 4 is larger than the width W of the glitch. FIG. 6 shows the timings of each of the signals when the delay time t2 of the circuit shown in FIG. 4 is smaller than or equal to the width W of the glitch. As can be seen from FIG. 5 and FIG. 6, when the delay time t2 is larger than the width W of the glitch, the negative glitch suppressing circuit filters the negative glitches in the input signal S, as a result, an output signal V without any negative glitches is obtained. However, under the circumstance that the delay time t2 is smaller than or equal to the width W of the glitch, the negative glitch suppressing circuit cannot efficiently filter the negative glitches in the input signal S, as a result, the output signal V still has negative glitch noises.
The aforementioned glitch suppressing circuits both have their limits in filtering noises, but such circumstances can be improved by adjusting the delay time. Generally, in order to suppress both the positive glitches and the negative glitches when both of them exist, the positive glitch suppressing circuit and the negative glitch suppressing circuit are successively connected in series, so as to filter the positive glitches and the negative glitches in the signal, as shown in FIG. 7.
FIG. 7 shows a conventional glitch suppressing apparatus. Referring to FIG. 7, the glitch suppressing apparatus includes a positive glitch suppressing circuit 710 and a negative glitch suppressing circuit 720. The positive glitch suppressing circuit 710 is identical to the circuit shown in FIG. 1, and the negative glitch suppressing circuit 720 is identical to the circuit shown in FIG. 4. The positive glitch suppressing circuit 710 receives an input signal IN, filters the positive glitches in the input signal IN, and then outputs the input signal IN into the negative glitch suppressing circuit 720 to filter the negative glitches in the input signal IN, and finally, an output signal OUT free of glitches is output.
However, such method of integrating the two mechanisms requires two circuits, one for suppressing positive glitches, and the other for suppressing negative glitches. Therefore, if such glitch suppressing apparatus is adopted in a chip, a large area on the chip is required.